1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level.
2) Description of the Prior Art
Semiconductor applications require increasing packaging density. To accomplish the increased density, device geometries are scaled. Line widths are reduced and the number of levels is increased. As line widths decrease and the number of interconnecting levels increase, it becomes increasingly difficult to form conductor lines and contacts using conventional fabrication methods.
One problem which limits scaling is mask alignment. When more than one mask is used to fabricate a semiconductor, device sizes must be larger than theoretically required to compensate for misalignment between masks. With each additional mask, the alignment tolerances are increased.
Another problem which limits scaling is the errors induced by variations in exposure during phtolithography caused by uneven surface topography.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,316,975 (Maeda) shows a method for an interconnect process.
U.S. Pat. No. 5,316,957 (Spratt et al.) discloses a process for fabricating a bipolar transistor with a recessed contact.
U.S. Pat. No. 5,283,201 (Tsang et al.) teaches a contact process for a recessed gate formed in a trench on a substrate.
U.S. Pat. No. 5,087,584 (Wada et al.) shows a process for forming a floating gate memory array using a wordline trench.
U.S. Pat. No. 5,082,795 (Temple) shows a FET with a self aligned structure.